Integrated circuit devices such as field programmable gate array (FPGA) devices are known to suffer bottlenecks that prevent high-speed boot-up by causing less than optimal configuration random access memory (CRAM) programming time. Accordingly, applications that require boot-up time that is faster than a programming time offered in a programmable integrated circuit device, such as an FPGA device, cannot be implemented in such a device. Typically, these bottlenecks are formed because configuration time is not scalable in conventional programmable integrated circuit devices, and therefore, the larger the device required to run an application, the larger the configuration time per data frame becomes. For example, as FPGA designs are scaled larger, data lines and address lines become larger, thus requiring more time to be configured.